The Limits of Copper in AI Data Centers
AI workloads are scaling faster than the interconnects that feed them. Copper traces between the switch ASIC and the front-panel optics draw power the rack budget no longer has, and usable reach shortens with every jump in lane rate. Co-packaged optics moves the optical engine alongside the ASIC and cuts the electrical path to millimeters, which changes the power equation for the whole switch.
Building those modules is the harder half. Hundreds of single-mode fibers and polarization-maintaining laser lines have to land on the perimeter of a single chiplet within sub-micron tolerance, at volumes legacy alignment methods cannot reach. This paper explains where the power savings come from and how multichannel active alignment makes co-packaged optics manufacturable at production rates.
